Complementary low power non-volatile reconfigurable EEcell
US5272368A · kind A · utility
112Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 10, 1991 |
| Grant date | Dec 21, 1993 |
| Priority date | — |
| Expiry date | May 10, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile CMOS electrically erasable programmable memory cell for configuring a PLD is disclosed. A CMOS inverter is formed by fabricating an n-channel MOSFET and a p-channel MOSFET with merged floating gate regions. A tunnel capacitor allows charge to be supplied to or removed from the floating gate. The floating gate provides non-volatile charge storage. The CMOS inverter senses the presence or absence of charge on the floating gate and provides an amplified inverted output. The CMOS inverter consumes very low power and provides rail-to-rail output voltage swings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.