Patent · US Expired

Circuit limiting the load current of a power MOSFET

US5272399A · kind A · utility

20Cited by

2References

5Claims

0Family size

Assignee

Siemens Aktiengesellschaft · DE

Inventors

Jenoe Tihanyi · Tauberbischofsheim, DE
Ludwig Leipold · Munich, DE
Rainald Sander · Oberhaching, DE

Key dates

Filing date	Jan 15, 1993
Grant date	Dec 21, 1993
Priority date	—
Expiry date	Jan 15, 2013

Classification

Technology area (CPC H)Electricity
CPC primaryH03K17/0822
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A circuit configuration for limiting current flowing through a power MOSFET includes a voltage divider being connected between drain and source terminals of the power MOSFET and having a node at which a voltage following a drain-to-source voltage of the power MOSFET drops. A control transistor has a load path connected between the gate terminal and the source terminal of the power MOSFET. The control transistor is made conducting as a function of the voltage at the node of the voltage divider if the drain-to-source voltage of the power MOSFET exceeds a predetermined value. A resistor is connected between the gate terminal of the control transistor and the gate terminal of the power MOSFET. A depletion FET has a drain terminal connected to the gate terminal of the control transistor. The source terminal of the depletion FET is connected to the node of the voltage divider. The gate terminal of the depletion FET is connected to the source terminal of the power MOSFET.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.