Finite field parallel multiplier
US5272661A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1992 |
| Grant date | Dec 21, 1993 |
| Priority date | — |
| Expiry date | Dec 15, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/724
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A finite field parallel multiplier in GF(q.sup.m) including a router for directing 2m-1 components in m groups of m single-component signal lines towards m computing circuits for performing multiply and add modulo-q. The router guides m components from a first finite field element along with an additional m-1 components generated from linear combinations of the m components of the first finite field element. Each of the computing circuits receives all of the components from the second finite field element and m components provided by one set of signal lines through the router. Each computing circuit generates a single component for the resultant finite field element. These resulting components may be input through a basis change circuit to obtain a result in the desired basis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.