High performance lateral PNP transistor with buried base contact
US5273913A · kind A · utility
4Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 23, 1992 |
| Grant date | Dec 28, 1993 |
| Priority date | — |
| Expiry date | Nov 23, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28525
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high performance PNP lateral bipolar transistor is described, incorporating at least two trenches extending from the upper P.sup.- surface of a semiconductor substrate almost to a buried N.sup.+ layer. The floor of one trench is heavily N-doped to establish a connection between the buried N.sup.+ layer and an N.sup.- diffusion in the walls of the trench. When the trenches are backfilled with P.sup.+ polysilicon a lateral PNP is formed having a buried base contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.