Floating channel field effect transistor and a fabricating method thereof
US5274257A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1992 |
| Grant date | Dec 28, 1993 |
| Priority date | — |
| Expiry date | Aug 7, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/221
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A field effect transistor is disclosed in which a source region and a drain region are formed to be reverse mesa on a semi-insulating semiconductor substrate with an insulating layer thereon by using a crystal growth characteristic corresponding to the crystal orientation. A channel layer and a gate electrode are formed by self-alignment on the upper part of a void formed according to the reverse mesa of the source and the drain regions, so that the channel layer and the semiconductor substrate are electrically separated by the void. By such a construction, a leakage current and backgating effect are removed, and a fast field effect transistor is attained owing to the reduction of an effective channel length and a gate resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.