"High speed ""OR"" circuit configuration"
US5274277A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 1, 1992 |
| Grant date | Dec 28, 1993 |
| Priority date | — |
| Expiry date | Sep 1, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09448
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for providing an OR function on the outputs of at least two MOS logic circuits. The circuit has an output node capable of being in a first or second logic state and being responsive to a first or second path. The first path includes multiple WIRED-OR logic circuits which function as an OR gate on the outputs of MOS logic circuits. The results of the operation cause the architecture output to transition into the first state. The second path is skewed for the second state, such that the transition into the second state occurs fast. Thus, the transition of the output node from the second state to the first state and vice versa is provided by one path, such that the overall ORing function occurs faster.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.