Monostabilized dynamic programmable logic array in CMOS technology
US5274282A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1992 |
| Grant date | Dec 28, 1993 |
| Priority date | — |
| Expiry date | Oct 30, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17716
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The circuit includes an input register (RI); an output register (RU); an AND plane; and an OR plane. The AND plane has vertical lines (Y), which are controlled by the input register, and horizontal lines (L), which include transistors (TA) arranged in series and controlled by respective vertical lines. The horizontal lines are connected to ground by normally-off transistors (TV) and to the power supply by normally-on transistors (TP). These transistors (TV, TP) are controlled by a first clock signal (CK1.about.). The OR plane has horizontal lines (S) and vertical lines (U). The vertical lines (U) of the OR plane contain normally-off transistors (TO) which are controlled by respective horizontal lines of the OR plane. Horizontal lines of the AND plane and horizontal lines of the OR plane are connected by respective pairs of normally-on transistors (TB) and normally-off transistors (TC) arranged in series between the power supply and ground. In each pair, the normally-on transistor is controlled by a horizontal line of the AND plane, and the normally-off transistor is controlled by a second clock signal (CK2). A horizontal line of the OR plane is connected to the node between the pai…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.