Analog-to-digital converter having multi-bit cascaded sigma-delta loops with delaying intergrators
US5274374A · kind A · utility
8Cited by
2References
4Claims
0Family size
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Key dates
| Filing date | Mar 20, 1992 |
| Grant date | Dec 28, 1993 |
| Priority date | — |
| Expiry date | Mar 20, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/416
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-bit cascaded sigma-delta A/D converter (40) has a higher resolution, higher sample rate, and lower harmonic distortion than previous multi-bit cascaded sigma-delta approaches. The A/D converter employs delaying switched capacitor integrators to relax settling time requirements and to thereby ease op amp design for multi-bit cascaded sigma-delta A/D converters. The converter has a true sample and hold input; the op amp amplifies a fixed amount of charge; and nodes are settled with the dc gain of the op amp, permitting greater settling accuracy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.