Circuit and method for normalizing detector circuit
US5274578A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 1992 |
| Grant date | Dec 28, 1993 |
| Priority date | — |
| Expiry date | Mar 12, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/21
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A dynamic detector normalization circuit for normalizing detector output data using detector-error-correcting offset and gain coefficients that are updated in real time. The offset/gain coefficients are computed by a coefficient processor (20) at selected update intervals based on detector responses to a reference source. The coefficient processor averages detector reference responses over a number of update intervals to obtain updated offset/gain coefficients with greater precision than that available from the detector network. The detector normalization circuit (10) includes offset addition logic (12) and gain coefficient logic (14) for reading-out the offset/gain coefficients stored in respective RAMs (13, 15). For each detector output sample received by the detector normalization circuit (10), an offset addition operation 40 adds to the sample the MS bits of the offset coefficient. After the addition operation, the LS bits of the offset coefficient (representing increased precision available from the offset coefficient) are concatenated, and after underflow/overflow protection (42), an offset-corrected detector sample is obtained. A gain multiplication operation (50) multiplies…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.