Look up table implementation of fast carry for adders and counters
US5274581A · kind A · utility
137Cited by
9References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 8, 1992 |
| Grant date | Dec 28, 1993 |
| Priority date | — |
| Expiry date | May 8, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Look up tables for use in programmable logic devices are modified to facilitate use of those tables to provide adders (including subtracters) and various types of counters. Each look up table is effectively partitioned into smaller look up tables when an adder or counter is required. One portion of the partitioned table is used to provide a sum out signal, while the other portion of the partitioned table is used to provide a fast carry out signal for application to the next stage of the adder or counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.