Semiconductor memory device capable of driving divided word lines at high speed
US5274597A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1991 |
| Grant date | Dec 28, 1993 |
| Priority date | — |
| Expiry date | Sep 30, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A divided word line driving circuit applicable to a static random access memory (SRAM) employing a divided word line method is disclosed. When a divided word line is activated, the potential at the input of an inverter for driving the word line is brought to a low level. When the input signals S1 and S2 are both at a low level, the divided word line is brought to an inactive state. The input of the inverter is charged by a transistor 101 in addition to a transistor 102 which is always on. In other words, transistor 101 contributes to accelerating charging of the input of the inverter. Consequently, the potential of the divided word line is made to rise at high speed, so that access operation at high speed can be achieved. The circuit is implemented with a small number of transistors, so that it becomes also possible to enhance the degree of integration of a SRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.