Clock recovery circuit with memory storage level comparison with high, medium and low thresholds
US5274681A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 1992 |
| Grant date | Dec 28, 1993 |
| Priority date | — |
| Expiry date | Mar 27, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/85
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A coded image signal is received and stored into a first-in-first-out memory on a bit-parallel word basis and the storage level of the memory is compared with high, medium and low threshold values. A first positive trimming value is generated when the storage level is higher than the high threshold, a second positive trimming value when it lies between the high and medium thresholds, a first negative trimming value when it is lower than the low threshold, and a second negative trimming value when it lies between the low and medium thresholds. Differential sampling clock rate is received and combined with each trimming value in an adder whose output is subtractively combined with a frequency variation of the line clock rate to produce a corrected differential sampling and line clock rate. The latter is integrated to produce a frequency control signal that drives a voltage-controlled oscillator whose output is used to drive the memory for reading the coded image signal on a bit-parallel word basis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.