System and method for compiling a fine-grained array based source program onto a course-grained hardware
US5274818A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1992 |
| Grant date | Dec 28, 1993 |
| Priority date | — |
| Expiry date | Feb 3, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8092
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a parallel vector machine model for building a compiler that exploits three different levels of parallelism found in a variety of parallel processing machines, and in particular, the Connection Machine.RTM. Computer CM-2 system. The fundamental idea behind the parallel vector machine model is to have a target machine that has a collection of thousands of vector processors each with its own interface to memory. Thus allowing a fine-grained array-based source program to be mapped onto a course-grained hardware made up of the vector processors. In the parallel vector machine model used by CM Fortran 1.0, the FPUs, their registers, and the memory hiearchy are directly exposed to the compiler. Thus, the CM-2 target machine is not 64K simple bit-serial processors. Rather, the target is a machine containing 2K PEs (processing elements), where each PE is both superpipelined and superscalar. The compiler uses data distribution to spread the problem out among the 2K processors. A new compiler phase is used to separate the code that runs on the two types of processors in the CM-2; the parallel PEs, which execute a new RISC-like instruction set called PEAC, and t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.