Low temperature crystallization and patterning of amorphous silicon films on electrically insulating substrates
US5275851A · kind A · utility
404Cited by
2References
12Claims
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Key dates
| Filing date | Mar 3, 1993 |
| Grant date | Jan 4, 1994 |
| Priority date | — |
| Expiry date | Mar 3, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02672
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabrication process polycrystalline silicon thin film transistors commences with the deposition of an ultra-thin nucleating-site forming layer onto the surface of an insulating substrate (e.g., 7059 glass). Next, an amorphous silicon film is deposited thereover and the combined films are annealed at temperatures that do not exceed 600.degree. C. By patterning the deposition of the nucleating site forming material on the glass substrate, the subsequently deposited amorphous film can be selectively crystallized only in areas in contact with the nucleating-site forming material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.