Method of forming stacked conductive and/or resistive polysilicon lands in multilevel semiconductor chips and structures resulting therefrom
US5275963A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 1991 |
| Grant date | Jan 4, 1994 |
| Priority date | — |
| Expiry date | Jul 12, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure including: a semiconductor substrate (18/19) having active regions (21) of devices (T1, . . . ) therein and/or polysilicon lines (23-1, . . .) formed thereupon; a first thick passivating layer (26/27) formed above the substrate having a set of first metal contact studs (30-1, . . .) therein contacting at least one of the active regions (21) and/or the polysilicon lines (23-1, . . . ); the surface of the first contact studs is coplanar with the surface of the first passivating layer; a plurality of polysilicon lands (31-1, . . .) formed on the planar structure in contact with the first contact studs; the polysilicon lands are either highly resistive, highly conductive or a mix thereof; a second thick passivating layer (34/35) formed above the resulting structure having a set of second metal contact-studs (37-1 . . .) therein contacting at least one of the polysilicon lands and/or one of the first contact studs; the surface of the second contact studs is coplanar with the surface of the second thick passivating layer. a plurality of metal lands (38-1, . . . ) formed above the second thick passivating layer (34/35) in contact with the second contact studs; a …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.