Implementation architecture for performing hierarchical motion analysis of video images in real time
US5276513A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1992 |
| Grant date | Jan 4, 1994 |
| Priority date | — |
| Expiry date | Jun 10, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/537
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
First circuit apparatus, comprising a given number of prior-art image-pyramid stages, together with second circuit apparatus, comprising the same given number of novel motion-vector stages, perform cost-effective hierarchical motion analysis (HMA) in real time, with minimum system processing delay and/or employing minimum hardware structure. Specifically, the first and second circuit apparatus, in response to relatively high-resolution image data from an ongoing input series of successive given pixel-density image-data frames that occur at a relatively high frame rate (e.g., 30 frames per second), derives, after a certain processing-system delay, an ongoing output series of successive given pixel-density vector-data frames that occur at the same given frame rate. Each vector-data frame is indicative of image motion occurring between each pair of successive image frames.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.