Semiconductor memory with reduced peak current
US5276645A · kind A · utility
3Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1992 |
| Grant date | Jan 4, 1994 |
| Priority date | — |
| Expiry date | Apr 2, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory has sense amplifiers coupled to complementary pairs of bit lines. A first switching element couples the sense amplifiers to a first potential, so that the sense amplifiers can bring one bit line in each pair of bit lines from a precharged state to the first potential. A second switching element couples the sense amplifiers to a shunt node. A third switching element couples the shunt node to the first potential. A capacitor capacitively couples the shunt node to a second potential different from the first potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.