Method and apparatus for clock recovery in digital communication systems
US5276712A · kind A · utility
21Cited by
19References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 16, 1989 |
| Grant date | Jan 4, 1994 |
| Priority date | — |
| Expiry date | Nov 16, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/027
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A technique for recovering a clock from a digitally encoded communication signal uses a low-Q resonator and limiter for generating a coarse clock signal comprising a series of rectangular pulses at a frequency substantially equal to the clock (though subject to phase jitter), and a filter circuit, such as a phase-locked-loop ("PLL"), preferably employing a Sequential Phase/Frequency Detector, to reduce the jitter superimposed on the coarse clock signal, so as to yield a well-behaved clock signal. By using a Sequential Phase/Frequency Detector, acquisition-aid circuitry generally is not required for the PLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.