Patent · US Expired

Digital neural network executed in integrated circuit technology

US5276773A · kind A · utility

8Cited by
4References
14Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 3, 1989
Grant dateJan 4, 1994
Priority date
Expiry dateJul 3, 2009

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06N3/063
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A digital neural network has a plurality of neurons (NR) completely meshed with one another, each of which comprises an evaluation stage having a plurality of evaluators (B) that is equal in number to the plurality of neurons (NR) and each of which comprises a decision stage having a decision unit (E). An adjustment information (INF.sub.E) that effects a defined pre-adjustment of the decision unit (E) can be supplied to every decision unit (E) by a pre-processing means via an information input. A weighting information (INF.sub.G) can be supplied to every evaluator (B) by a pre-processing means via an individual information input. An output information (INF.sub.A) can be output by every decision unit (E) to a post-processing means via a respective individual information output. The information outputs of the decision units (E) are each connected to an individual processing input of all evaluators (B) allocated to the appertaining decision unit (E). Individual processing outputs of the evaluators (B) are connected to individual processing inputs of the decision unit (E) in the appertaining neuron (N), so that every output information (INF.sub.A) can be indirectly fed back onto every …

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.