Method and apparatus for capturing real-time data bus cycles in a data processing system
US5276809A · kind A · utility
8Cited by
9References
9Claims
0Family size
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Key dates
| Filing date | Jun 26, 1990 |
| Grant date | Jan 4, 1994 |
| Priority date | — |
| Expiry date | Jun 26, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/25
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for implementing a capture of a long contiguous chain of data bus cycles for the memory system of a data processing system with memory units that alternate between real time capture of segments of the chain of data bus cycles and processing of the data bus signals in the captured segments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.