Data processor having a multi-stage instruction pipe and selection logic responsive to an instruction decoder for selecting one stage of the instruction pipe
US5276824A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 1993 |
| Grant date | Jan 4, 1994 |
| Priority date | — |
| Expiry date | Jun 21, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor having a microsequencer which reduces power consumption selectively activates instruction decode units and a microcode sequence control memory unit. The microsequencer has an instruction decode unit implemented with a plurality of PLAs and also has a microcoded ROM for providing the next microaddress. The instruction decode unit outputs a next microaddress, a next-PLA field, and a ROM-or-PLA control bit. The control bit functions to minimize power in the data processor. The next-PLA field is latched and used to select a single decode unit when the next instruction decode is needed to activate a predetermined decode unit. Early macroinstruction branching can be performed in the data processor thereby improving performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.