Protection system for critical memory information
US5276844A · kind A · utility
15Cited by
19References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 5, 1991 |
| Grant date | Jan 4, 1994 |
| Priority date | — |
| Expiry date | Aug 5, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG07B2017/00403
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A computer system, typically a postage member system, has a processor, a memory, an address decoder, and a window circuit. The window circuit selectively couples the write strobe output of the processor with the write strobe input of the memory in response to the processor's setting and clearing of a latched signal. A counter resets the processor if the latched signal is set and not cleared within a predetermined time period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.