Shared two level cache including apparatus for maintaining storage consistency
US5276848A · kind A · utility
141Cited by
10References
1Claims
0Family size
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Key dates
| Filing date | Aug 20, 1991 |
| Grant date | Jan 4, 1994 |
| Priority date | — |
| Expiry date | Aug 20, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multilevel cache buffer for a multiprocessor system in which each processor has a level one cache storage unit which interfaces with a level two cache unit and main storage unit shared by all processors. The multiprocessors share the level two cache according to a priority algorithm. When data in the level two cache is updated, corresponding data in level one caches is invalidated until it is updated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.