Automatic writeback and storage limit in a high-performance frame buffer and cache memory system
US5276851A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1992 |
| Grant date | Jan 4, 1994 |
| Priority date | — |
| Expiry date | Nov 6, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a plurality of central processing units (CPUs) each of which has a direct napped cache memory. The system also includes a main memory, and one or more display frame buffers. The cache normally operates in a write back mode, whereby updated data is written back to main memory only when a cache block is reallocated to store a new block of data. A tag for each block of data stored in the cache includes a Shared flag which indicates whether the corresponding block of data may be stored in the cache of another CPU. When a block of data stored is modified, it is immediately written to main memory if the tag for that block has an enabled Shared flag. To make the cache operate in a write-through mode for blocks of image data, the system stores an enabled Shared flag in the cache whenever a block of frame buffer data is stored in the cache. A circuit in the cache detects when the CPU is writing an entire block of image data to an address in the frame buffer and causes the cache to write the block of image data directly to the frame buffer without storing the image data in the cache. An address circuit in the cache stores image data from the frame buffer only in a …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.