Memory controller flexible timing control system and method
US5276856A · kind A · utility
18Cited by
13References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1989 |
| Grant date | Jan 4, 1994 |
| Priority date | — |
| Expiry date | Sep 28, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed a system and method of controlling the timing in a system having a number of different elements, each requiring individual timing signals. The system utilizes a RAM memory divided into a number of groups or cycle types, each cycle type having a number of addressable words. The individual bits of each word serve to control the individual system elements. The memory is programmed to allow each group of words to control the system timing in a different manner. Provision is made for the memory to skip certain words in a particular group under control of externally provided signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.