Data processing system with shared control signals and a state machine controlled clock
US5276857A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 1991 |
| Grant date | Jan 4, 1994 |
| Priority date | — |
| Expiry date | Apr 26, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data processing units (14) within an integrated circuit (10) are connected by a common bus (16). Each data processing unit follows a predetermined protocol for communicating to other data processing units via the common bus (16). Further, predetermined control and/or data processing signals within the common bus (16) are multi-tasked (i.e. function multiplexed) for a normal and special modes of operation. A state machine (21) within each data processing unit (12) controls a clock circuit (23). The state machine (21) has a predetermined state diagram for controlling clock signals associated with the predetermined modes of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.