Safestore frame implementation in a central processor
US5276862A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 1991 |
| Grant date | Jan 4, 1994 |
| Priority date | — |
| Expiry date | Apr 9, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1637
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In order to gather, store temporarily and deliver (if needed) central processor safestore information, a multiphase clock is employed to capture (one full clock cycle behind) the safestore information which typically includes all software visible registers in all (or selected) data manipulation chips of the CPU by routing the safestore information through temporary storage (under the influence of the multiphase clock) in a cache data array and into a special purpose XRAM module. Thus, upon the sensing of a fault, valid safestore information is available in the XRAM for analysis and, if appropriate, resumption of operation at a sequential point just previous to that at which the fault occurred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.