Hardware semaphores in a multi-processor environment
US5276886A · kind A · utility
44Cited by
4References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 11, 1990 |
| Grant date | Jan 4, 1994 |
| Priority date | — |
| Expiry date | Oct 11, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer system having at least two processors, each processor having an associated memory, the processors being coupled to one another through an interface unit by means of a bus, hardware semaphores to regulate access to shared resources are disclosed. Each semaphore is one bit wide and can be written to obtain the desired state. When reading the semaphore, if the contents is a one, then a one is returned. If the content is zero, a zero is returned but the semaphore is automatically reset to one.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.