Matrix addressable displays
US5278086A · kind A · utility
1Cited by
5References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 27, 1990 |
| Grant date | Jan 11, 1994 |
| Priority date | — |
| Expiry date | Nov 27, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2202/104
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
In a method of forming a matrix addressable display comprising a group of switchable cells, such as liquid crystal cells, having electrodes on each of two parallel plates and thin-film drive transistors disposed on one of the plates, gate resistors are provided by elongate doped polysilicon regions connecting the gate electrodes to address lines. The gate resistors prevent short-circuiting of the address lines in the event of a gate short-circuit occurring in any of the transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.