Self-biasing input stage for high-speed low-voltage communication
US5278467A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 14, 1992 |
| Grant date | Jan 11, 1994 |
| Priority date | — |
| Expiry date | Jul 14, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/023
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit that includes a self-biased differential amplifier a level restore circuit. The output of the differential amplifier is coupled to the source pins of a p type transistor and an n type transistor. The output of the differential amplifier is further coupled to a first inverter circuit that provides feedback to the gates of the p and n type transistors. The first inverter also further amplifies the output voltage of the differential amplifier. When the differential amplifier outputs a high voltage, the p transistor attempts to drain the output and pull the output voltage down. When the differential amplifier begins switching from a high voltage to a low voltage, the p transistor accelerates the voltage swing and decreases the propagation delay of the buffer circuit. Likewise, when the differential amplifier swings from a low voltage to a high voltage, the n type transistor reduces the propagation delay of the voltage swing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.