Method and apparatus for partially overmolded integrated circuit package
US5278726A · kind A · utility
100Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 22, 1992 |
| Grant date | Jan 11, 1994 |
| Priority date | — |
| Expiry date | Jan 22, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A partially overmolded integrated circuit package (10) comprises a substrate (14) having circuit traces (11) and a semiconductor die receiving area (15) for attachment of a semiconductor die to the semiconductor die receiving area. Conductive bumps (18) are then applied to a plurality of contact pads on the semiconductor die. Then overmolding compound (16) is applied over the semiconductor die and a portion of the conductive bumps, leaving a portion of the conductive bumps partially exposed (19). Finally, interconnections (13) between the exposed portion of the conductive bumps and the circuit traces of the substrate are formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.