Memory circuit having a line decoder with a Darlington-type switching stage and a discharge current source
US5278795A · kind A · utility
1Cited by
12References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 16, 1990 |
| Grant date | Jan 11, 1994 |
| Priority date | — |
| Expiry date | Aug 16, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a memory having a line decoder provided with a Darlington-type switching stage. When the deselection time T.sub.1 of a line is notably shorter than the intrinsic switching time T.sub.3 of a memory cell (M11 . . . Mnp), a discharge current I.sub.D is temporarily applied to the lower line conductor (1' . . . n') of the line (L1 . . . Ln) which is deselected. To achieve this, the current source I.sub.D is connected to said lower line conductors (1' . . . n') via delay circuits (RL1, DL1 . . . RLn, DLn) having a time constant T.sub.2 which is smaller than T.sub.3 and at least equal to T.sub.1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.