Data transfer circuit for interfacing two bus systems that operate asynchronously with respect to each other
US5278957A · kind A · utility
55Cited by
12References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 16, 1991 |
| Grant date | Jan 11, 1994 |
| Priority date | — |
| Expiry date | Apr 16, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for transferring data from one bus system to another is disclosed. The circuit allows the write bus to perform write operations indiscriminately of any handshaking, wait states or other control signals which would otherwise reduce the bus efficiency of the system. Similarly, the read bus system has no handshaking or wait states but is provided with a data ready signal to indicate when valid data may be read. This circuit is used in applications where less than 100% data integrity is permissible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.