Microprocessor system including a cache controller which remaps cache address bits to confine page data to a particular block of cache
US5278964A · kind A · utility
11Cited by
6References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1993 |
| Grant date | Jan 11, 1994 |
| Priority date | — |
| Expiry date | Jan 4, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache controller for a set associative cache selectively remaps predetermined bits of the cache address so as to confine data from a single memory page to a particular block of the cache memory. When changing a memory page, only the particular block of the cache in which data from that page may be stored is flushed, thereby preserving the remaining contents of the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.