Method and apparatus for the dynamic adjustment of data transfer timing to equalize the bandwidths of two buses in a computer system having different bandwidths
US5278974A · kind A · utility
25Cited by
21References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 4, 1989 |
| Grant date | Jan 11, 1994 |
| Priority date | — |
| Expiry date | Dec 4, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The bandwidth of a first bus and a second bus, unequal due to differences in protocol overheads and cycle times between the buses, are equalized without sacrificing any bandwidth on the lower bandwidth bus and without introducing any buffering in a control logic device. The control logic device equalizes the bandwidths of the buses by instructing a device coupled to the second bus to insert a partial dead bus cycle in a read transmission thereby dynamically adjusting read timing on the second bus when the second bus is heavily loaded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.