Implementation of the IEEE 1149.1 boundary-scan architecture

US5281864A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Reinhard Hahn · Vilsheim, DE
• Norbert Hummer · Forchheim, DE

Key dates

• Filing date: Apr 10, 1992
• Grant date: Jan 25, 1994
• Expiry date: Apr 10, 2012

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318541
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A circuit for a boundary-scan cell for the JTAG Architecture, the circuit including a capture section(50) coupled in cascade to an update section(52), and each section comprising a flip-flop (34,36)having a clock input for receiving a common clock signal (TCK, TCKB) and a multiplexer having a first input for receiving an input data signal, a second input coupled to an output of the flip-flop, an output coupled to a flip-flop input, and a select input for receiving a control signal for selectively coupling the first or second input to the multiplexer output.