Phase locked loop made operative when stable input sync signal is detected
US5281926A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 6, 1992 |
| Grant date | Jan 25, 1994 |
| Priority date | — |
| Expiry date | Oct 6, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/126
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An oscillator control system includes a phase-locked loop having a programmable frequency divider operative within the loop. A switch is further included within the phase-locked loop to permit the loop to be open or closed in response to an input signal. A counter accumulates oscillator clock signal counts between each successive rising edge portion of the applied sync signal. A pair of shift registers sequentially store successive clock signal counts for the current and previous sync signal intervals. The output counts are compared for consistency by producing a difference signal therebetween which is utilized to control the phase-locked loop switch and close it once the consistency of sync signal has been established. The output counts of the shift registers are combined and used to provide a scaling factor which sets the frequency division of the programmable frequency divider within the phase-locked loop and properly scales the oscillator frequency to the sync signal frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.