Method and apparatus for optimizing a logic network
US5282147A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 1991 |
| Grant date | Jan 25, 1994 |
| Priority date | — |
| Expiry date | Aug 2, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for optimizing a logic network including expressing the logic network as an original graph having vertices, edges which connect the vertices and which represent connections in the logic network, and inversion markings for representing inverters in the logic network; determining a fundamental cycle(s) in the original graph; sorting the determined fundamental cycle(s) according to its parity; forming a final graph by processing the fundamental cycle(s) so as to optimize inverter placement therein while maintaining the parity thereof; comparing the inversion markings of the original and final graphs to determine a set of transformation locations in the logic network; and re-configuring the logic network in accordance with the determined transformation locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.