Synchronization circuit for establishing frame synchronism using pointers in a digital transmission system
US5282206A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 1992 |
| Grant date | Jan 25, 1994 |
| Priority date | — |
| Expiry date | Dec 3, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J2203/0089
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A synchronous circuit includes a first circuit block operating in synchronism with a first clock signal, and a second circuit block operating in synchronism with a second clock signal having a frequency lower than that of the first clock signal. The first circuit block includes a frame synchronizing circuit for detecting a synchronous pattern contained in input data having a frame format having a supervisory control data part and an information part, the supervisory control data part including pointer information indicative of a beginning of the information part. The first circuit block includes a synchronizing unit for generating, from the synchronous pattern, a synchronizing control signal for synchronizing the operation of the second circuit block with the operation of the first circuit block. The first circuit block includes a pulse generator for generating a first frame pulse signal from the first clock signal. The second circuit block includes an information part detecting unit for generating a second frame pulse signal having a frequency lower than that of the first frame pulse signal from the second clock signal and the synchronizing control signal, the first frame pulse si…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.