Interrupt distribution scheme for a computer bus
US5282272A · kind A · utility
96Cited by
19References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 28, 1993 |
| Grant date | Jan 25, 1994 |
| Priority date | — |
| Expiry date | Jan 28, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of handling processor to processor interrupt requests in a multiprocessing computer bus environment is described. This method allows a multiple-tiered, increasing priority, interrupt request scheme. This method also allows processor to processor directed interrupt requests, processor to one processor of a group of processors interrupt requests, and processor to all processors of a group of processors interrupt requests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.