Semiconductor device including very low sheet resistivity buried layer
US5283454A · kind A · utility
14Cited by
2References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 11, 1992 |
| Grant date | Feb 1, 1994 |
| Priority date | — |
| Expiry date | Sep 11, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metal or silicide buried layer in MOS semiconductor devices provides a drain contact on the upper surface of the device with a greatly reduced resistance. The methods of manufacture include depositing the buried layer, rather than diffusing, so that interference with other components is greatly reduced and spacing between components is reduced to reduce the over-all size of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.