Programmable capacitance delay element having inverters controlled by adjustable voltage to offset temperature and voltage supply variations
US5283631A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 1991 |
| Grant date | Feb 1, 1994 |
| Priority date | — |
| Expiry date | Nov 1, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/747
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay element for fine tuning the position in time of timing edges of an input signal, comprising a first and a second inventer, each comprising a data input, a control input and a data output. The delay element further comprises a node comprised of a connection between the data output of the first inverter and the data input of the second inverter. An adjustable control voltage is included for applying a biasing voltage to the first and second control inputs to thereby control the amount of charge supplied to the node. Finally, the variable capacitance means is connected to the node for applying finite amounts of capacitance to the node to delay and thereby fine tune in time the timing edges of the input signal propagating from the first inverter to the second inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.