Method of fabricating a heterojunction bipolar transistor
US5284783A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 1991 |
| Grant date | Feb 8, 1994 |
| Priority date | — |
| Expiry date | Jul 2, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/936
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device having an epitaxial layer of a group III-V semiconductor material provided on an underlying crystal layer with a lattice matching therewith, the semiconductor material being doped to the p-type by addition of beryllium and selected from a group including gallium aluminum arsenide and indium gallium aluminum arsenide, in which the method comprises steps of growing the epitaxial layer on the underlying crystal layer, adding beryllium to a concentration level of about 5.times.10.sup.19 atoms/cm.sup.3 to about 5.times.10.sup.20 atoms/cm.sup.3 to the semiconductor material, and adding indium by an amount of about 0.5 mole percent to about 8 mole percent with respect to group III elements in the semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.