Method of making a split floating gate EEPROM cell
US5284786A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 14, 1992 |
| Grant date | Feb 8, 1994 |
| Priority date | — |
| Expiry date | Aug 14, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
Abstract
A split floating gate EEPROM memory cell formed in a P-type silicon substrate includes source and drain buried n+ diffusion regions formed in the silicon substrate to define a substrate channel region therebetween. A layer of floating gate oxide about 400.ANG. thick is formed over the source and drain regions and over the channel region. The floating gate oxide includes a region of thin tunnel oxide about 80-100.ANG. thick formed therein over the drain region. A floating gate is formed on the floating gate oxide to extend over the channel region and includes a portion that extends over the tunnel oxide. The floating gate comprises a first layer of polysilicon about 300-600.ANG. thick, a silicon dioxide layer about 20-50.ANG. thick formed on the first layer of polysilicon, and a second layer of polysilicon about 2000.ANG. thick formed on the silicon dioxide layer. A layer of ONO is formed on the floating gate and a polysilicon control gate is formed on the layer of ONO.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.