Array of field effect transistors of different threshold voltages in same semiconductor integrated circuit
US5285069A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 1991 |
| Grant date | Feb 8, 1994 |
| Priority date | — |
| Expiry date | Nov 21, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
Abstract
A semiconductor integrated circuit apparatus has a basic cell region formed by arranging a plurality of basic cells each including a MOS transistor in longitudinal and transversal directions. The MOS transistor has source-drain section diffusive regions formed on a semiconductor substrate, and a gate electrode formed on a channel region between these source-drain section diffusive regions through a gate insulating film. One portion or all of the channel region of at least one MOS transistor within the basic cell region has an impurity concentration different from that in the channel region of another MOS transistor of the same conductivity type within the same basic cell. For example, a threshold voltage in the channel region of a MOS transistor is increased until about 6 volts by implanting ions into the channel region. No MOS transistor is operated at a power voltage such as 5 volts and separates MOS transistors on both sides thereof from each other. Wiring is formed on the MOS transistor and the gate electrode is used as the wiring, thereby improving wiring efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.