Vertical insulated gate semiconductor device with less influence from the parasitic bipolar effect
US5285094A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1992 |
| Grant date | Feb 8, 1994 |
| Priority date | — |
| Expiry date | Jul 29, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0291
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a semiconductor device having an n-type semiconductor region forming one of the main surfaces of a semiconductor substrate, with a plurality of p-type semiconductor regions formed in the n-type semiconductor region. Two exposed n-type semiconductor regions are formed on each of the p-type semiconductor regions, with a main electrode formed on the n-type semiconductor regions and the exposed p-type semiconductor region therebetween. An insulated gate extends from one of the n-type semiconductor regions in one of the p-type semiconductor regions to a closer one of the n-type semiconductor regions in an adjacent p-type semiconductor region. The length of the insulated gate is longer than a distance between adjacent insulated gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.