High stability static memory device having metal-oxide semiconductor field-effect transistors
US5285096A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 1992 |
| Grant date | Feb 8, 1994 |
| Priority date | — |
| Expiry date | Sep 11, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
Abstract
A static memory device has memory cells each having a pair of driver MOSFETs, two load resistors each connected between a power source and a drain of each of the driver MOSFETs, two access MOSFETs each of which is connected between the drain of each of the driver MOSFETs and each of bit lines and gates of which are connected to a word line. In the memory cell, the thickness of a gate oxide film of the access MOSFET is made thicker than that of the gate oxide film of the driver MOSFET. The operation stability of the memory cell is enhanced, without the need of increasing a chip size, by increasing a ratio between the driver MOSFETs and the access MOSFETs of the memory cell (the ratio of current supplying capabilities of the two transistors) without making a gate size large or without making it so small as to cause process variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.