Method of forming a planarized insulation layer
US5285102A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 8, 1992 |
| Grant date | Feb 8, 1994 |
| Priority date | — |
| Expiry date | Dec 8, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/133
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a planar insulating layer over the surface of a semiconductor workpiece 8 which includes at least one low region 13 is discussed herein. The first step is to form a layer of blocking material 14 on the surface of the workpiece 8. A first material region 20 is then formed in the low region 13 and an insulating layer 21 is formed over the surface of the workpiece 8 including the first material region 20. The workpiece 8 is then heated in the presence of an active ambient such that the insulation layer 21 reflows and also so that the first material 20 region reacts with the active ambient to create an internal stress in said insulation layer 21. Other systems and methods are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.