Errorless line protection switching in asynchronous transer mode (ATM) communications systems
US5285441A · kind A · utility
131Cited by
3References
47Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1992 |
| Grant date | Feb 8, 1994 |
| Priority date | — |
| Expiry date | Mar 17, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5627
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An errorless line protection apparatus involves receipt of data from an active line and a standby line. A determination is made as to whether the data from the active line leads or lags the data on the standby line. A switching system directs the leading data to a lead channel containing a controllable amount of time delay up to the maximum amount that the leading data is expected to led the lagging data. Lagging data is directed to a lag channel. A selected one of the data from the lead channel or the lag channel is delivered to an output line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.