Phase synchronization circuit
US5285483A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1992 |
| Grant date | Feb 8, 1994 |
| Priority date | — |
| Expiry date | Jun 8, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Voltage controlled oscillator 40 has an oscillation stoppage cancelling circuit 46 and a current/frequency converter circuit 44 which is a ring oscillator made by connecting inverters forming 3 stages like a ring. Oscillation stoppage canceling circuit 46 stops and releases oscillation of the ring oscillator by a control signal RS. One-shot circuit 3 has a pulse width adjusting circuit 60 which is made by cascade-connecting the inverters constituting the ring oscillator of current/frequency converter 44 and inverters having the same characteristics in 3 stages. When the PLL enters a synchronization field, a synchronization field detector 1 issues a detection signal C and an input switch signal SC; a selector circuit 2 selects read data; and oscillation control signal RS starts upon the rise of a pulse S.sub.IN. Oscillation stoppage cancelling circuit 46 thus stops oscillator 40 and keeps an output V.sub.OUT at H level. After a few bytes of the synchronization bit have passed, detection signal C rises and oscillation control timing circuit 50 starts control signal RS upon the rise of the read data. Oscillation restarts, but the time at which the output V.sub.OUT falls from H level t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.